Method and System for a Low-Complexity Soft-Output MIMO Detection

ABSTRACT

An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2N T −1 (N T =number of transmit antennas) on-demand to only 2K−1 lowest Partial Euclidean Distance (PED) paths at last tree level 2N T . The relaxed LLR computation scheme includes approximating LLR computations by assuming that discarded path PED is greater than or equal K-Best path PED.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims benefit under 35 USC §119(e) of U.S.Application No. 61/349,752, filed May 28, 2010, entitled “Method andSystem for a Low-Complexity Soft-Output MIMO Detection” by DimpeshPatel, Mandi Shabany, and Glenn Gulak, the content of which isincorporated herein by reference in its entirety.

The present application is related to U.S. application Ser. No.12/786,288, filed May 24, 2010, entitled “Signal Processing Block for aReceiver in Wireless Communication”; the content of which isincorporated herein by reference in its entirety.

The following publications provide additional technical information inconnection with the present application:

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The present application incorporates herein by reference the entirecontents of all of the above publications.

BACKGROUND OF THE INVENTION

The present invention relates to multiple-input multiple-outputtechnology (MIMO) and more particularly to methods and systems for alow-complexity K-best detection.

Multiple-input multiple-output (MIMO) technology is employed in today'swireless digital communication systems to improve spectral-efficiencyand robustness to fading without increasing power or bandwidth. The termMIMO refers to communication systems that use an array of antennas atboth the transmitter and the receiver. In many wireless standards suchas IEEE 802.16m and LTE-Advanced, MIMO may be combined with channelcoding to further improve the system diversity. However, alow-complexity high-throughput VLSI implementation of near-optimum 4×4MIMO detectors has been a major design challenge for high-orderquadrature amplitude modulation (QAM) schemes. Near-optimum MIMOdetectors offer scalable complexity, while providing comparableperformance to the Maximum Likelihood (ML) detector. Depending on howMIMO detectors carry out the non-exhaustive search, they generally fallinto two main categories: depth-first and breadth-first search. Amongthe breadth-first search detectors, the K-Best algorithm guarantees anSNR-independent fixed throughput with performance close to ML.Furthermore, its feed-forward detection approach makes it particularlyattractive for pipelined VLSI implementation.

BRIEF SUMMARY OF THE INVENTION

In an embodiment of the present invention, a method for soft-outputK-Best MIMO detection includes computing an estimated symbol vector andLog-likelihood Ratio (LLR) values for transmitted bits. The methodfurther includes retaining, processing, and utilizing paths discardedfrom the intermediate tree levels, in addition to the exhaustivelyextended paths at the last tree level, to attain Bit Error Rate (BER)performance improvement. In addition, the method includes one or more ofthe following processes: a relevant discarded paths selection process, alast-stage on-demand expansion process, and a relaxed LLR computationprocess.

In an embodiment, the relevant discarded paths selection processincludes analyzing the K-Best paths and discarded paths at eachintermediate tree level, and selecting only those discarded paths forfurther processing that will help in LLR computation for at least one ofthe transmitted bits, so that the required number of path augmentation,partial Euclidean Distance (PED) computations and PED comparisons issignificantly reduced.

In an embodiment, the last-stage on-demand expansion process includesexpanding K paths (for K-Best algorithm) at the tree level 2N_(T)−1(N_(T) being the number of transmit antennas) on-demand to only 2K−1lowest PED paths at the last tree level 2N_(T), wherein the on-demandpath extension is configured such that these 2K−1 paths have the lowestPED values (to be directly utilized for LLR computation) among the totalK*√Q (where Q is the constellation order) paths, and that they aresorted in the order of ascending PED values, so that the number of pathaugmentations and PED computations is reduced from K*√Q to only 2K−1 andthe number of PED comparisons is reduced from K*√Q to 0.

In an embodiment, the relaxed LLR computation process includesapproximating LLR computations by making the assumption that discardedpath PED is greater than or equal K-best path PED, so that there is noPED comparisons required and that the relaxed LLR computation onlyresults in minor BER performance loss.

In an embodiment, a system for implementing the soft-output K-Best MIMOdetection includes a deeply pipelined and highly parallel architectureof a Soft-output K-Best MIMO detector. In an embodiment, the soft-outputK-best MIMO detector is used in a multiple-input and a multiple-output(MIMO) receiver system supporting quadrature amplitude modulations(M-QAM with M being an integer). The architecture is designed to be areaand power efficient, while offering high detection throughput. Throughphysical synthesis, the architecture has been proven to support errorcorrection codes (ECC) coded data rates up to 1 Gbps with a detectionthroughput of up to 2 Gbps; so that the system satisfies the aggressiverequirements of the latest 4G wireless standards such as IEEE 802.16mand LTE-Advanced.

In another embodiment, a soft-output K-Best MIMO detector includes aninput terminal configured to receive a vector Z and an upper-triangularmatrix R. The detector also includes a plurality of processing elementsarranged in a pipelined architecture. The pipelined structure contains anumber of levels that process the vector Z together with matrix R togenerate Log-likelihood ratio (LLR) values for transmitted bits. Thenumber of levels equals twice the number of transmit antennas in theMIMO system. In an embodiment, the plurality of processing elements areconfigured to retain selected discarded paths from intermediate levelswithin the total number of levels, compute Partial Euclidean Distance(PED) values in the intermediate levels utilizing the retained selecteddiscarded paths and sort the PED values.

In yet another embodiment, a device for soft-output K-Best MIMOdetecting for M-QAM MIMO receivers includes a multiplication block, aNote Bit Occurrences (NBO) block configured to populate bit occurrencetables using the current level K-Best paths and the accumulated selected(chosen) discarded paths from previous levels, a Tag Discarded Paths(TDP) block configured to tag a discarded path, a Fill_MinPEDTable_Iblock configured to populate a minimum PED table, and aFill_MinPEDTable_II block coupled to the Fill_MinPEDTable_I block andbeing configured update the minimum PED table using the selecteddiscarded paths. In an embodiment, the multiplication block performsmultiplication of one of the operands with any of −7, −5, −3, −1, +1,+3, +5 or +7 representing real and imaginary parts of a constellationsymbol using only one adder and 4 multiplexors, thus yielding very smallarea and power requirements and small critical path delay.

In an embodiment, the Note Bit Occurrences (NBO) block uses a pluralityof KB_NBO (K-Best NBO) sub-blocks and a plurality of DP_NBO (DiscardedPath NBO) sub-blocks. Each of the KB_NBO sub-blocks include a resetmechanism using logical OR and AND operations to reset the KB bitoccurrence table. Each of the DP_NBO sub-blocks includes a taggingmechanism using logical OR and AND operations to recognize and tag thebits that belong to the selected relevant discarded paths.

In an embodiment, the Tag Discarded Paths (TDP) block and its DP_TDPsub-block can detect whether the current discarded path will yielduseful information for LLR computation in the future and select (tag)the discarded path in the event that it is relevant.

In an embodiment, single bit sub-blocks of the Fill_MinPEDTable_I andthe Fill_MinPEDTable_II blocks use special reset mechanisms and othernovel architecture to reduce gate count and power consumptionrequirements.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following drawings, emphasis is placed upon illustrating theprinciples of the invention. The various embodiments and advantages ofthe present invention will be more fully understood when considered withrespect to the following detailed description, appended claims andaccompanying drawings wherein:

FIG. 1 is an error percentage plot of a relaxed LLR computation schemeaccording to an embodiment of the present invention;

FIG. 2 is a simplified block diagram of a 4×4 64-QAM Soft-output K-BestMIMO detector with K=10, in accordance with an embodiment of the presentinvention;

FIG. 3 shows a simplified single block diagram of a soft processingelement sub-block according to an embodiment of the present invention;

FIG. 4 is a simplified logic block diagram of a multiplication blockaccording to an embodiment of the present invention;

FIG. 5 is a simplified block diagram of a Note Bit Occurrences (NBO)block with critical path highlighted according to an embodiment of thepresent invention;

FIG. 6 is a simplified logic block diagram of a KB_NBO sub-blockaccording to an embodiment of the present invention;

FIG. 7 is a simplified logic block diagram of a DP_NBO sub-blockaccording to an embodiment of the present invention;

FIG. 8 is a simplified block diagram of a Tag Discarded Paths (TDP)block according to an embodiment of the present invention;

FIG. 9 shows a simplified logic block diagram of a DP_TDP sub-block fora single bit according to an embodiment of the present invention;

FIG. 10 is a simplified block diagram of a Fill_MinPEDTable_I blockaccording to an embodiment of the present invention;

FIG. 11 is a simplified single functional block diagram of aFill_MinPEDTable_II block with the critical path highlighted accordingto an embodiment of the present invention;

FIG. 12 is a a block diagram of a ComputeLLR Output Controller blockwith the critical path highlighted according to an embodiment of thepresent invention; and

FIG. 13 is a graph illustrating the BER performance of the presentinvention vs. conventional art for a 4×4 MIMO system with 64-QAM.

DETAILED DESCRIPTION OF THE INVENTION

The following notation is used throughout the present application.

Term Definition BER Bit Error Rate ECC Error Correction Code LLR LogLikelihood Ratio MIMO Multiple Input Multiple Output MKSE ModifiedK-best Schnorr-Euchner PED Partial Euclidean Distance QAM QuadratureAmplitude Modulation RVD Real-Value Decomposition SPE Soft ProcessingElement SNR Signal-to-Noise Ratio ZF Zero-Forcing

The following description is presented to enable a person skilled in theart to make and use the invention, and is provided in the context of aparticular application and its requirements. Various modifications tothe disclosed embodiments will be readily apparent to those skilled inthe art, and the general principles defined herein may be applied toother embodiments and applications without departing from the scope ofthe invention. Thus, the present invention is not intended to be limitedto the embodiments disclosed, but is to be accorded the widest scopeconsistent with the principles and features disclosed herein.

Before describing in detail embodiments that are in accordance with thepresent invention, it should be noted that the figures are for ease ofexplanation of the basic teachings of the present invention only. Thefigures being block diagrams or circuit diagrams provide only theconcept of the preferred embodiment of the invention. Further, the exactcircuit designs and the specifications of the passive and active devicesfor each of the functions described in the embodiments will be withinthe skill of the art after the following teachings of the presentinvention have been read and understood. The figures are represented bysymbols and nomenclature that are standard in the industry.

A complex N_(R)×N_(T) MIMO system can be modeled as an equivalent2N_(R)×2N_(T) real system using Real Value Decomposition (RVD):

Y=HS+V  (1)

Where S is the transmitted signal vector, Y is the received signalvector, H is the N_(R)×N_(T) channel matrix response, and V is theadditive White Gaussian Noise vector. The dimension of S, Y and H are2N_(T)×1, 2N_(R)×1 and 2N_(R)×2N_(T), respectively. Each symbol in S isdrawn from a symmetric M-QAM constellation Ω={−√M+1, . . . , −1, 1, . .. +√M−1}. Using QR-decomposition, the channel matrix H can be decomposedinto a unitary matrix Q and an upper-triangular 2N_(R)×2N_(T) matrix R.Performing a nulling operation on the received signal by Q^(H) resultsin the updated system equation:

Z=Q ^(H) Y=RS+Q ^(H) V  (2)

Where Q^(H) is the conjugate transpose of the matrix Q, i.e.,Q^(H)=(Q^(T))*.

The objective of the MIMO detection system is to find the closesttransmitted vector S based on the observation Y, such that the Euclideandistance ∥Z−RS∥² is minimized.

The Soft-output K-Best MIMO detection method and system are describedfor a 4×4 64-QAM system. It should be understood that the concept andarchitecture disclosed in this invention can be applied to any order(size) of quadrature amplitude modulation such as 16-QAM, 256-QAM or anyother order of QAM. In an embodiment of the present invention, a methodfor soft-output K-best MIMO detection computes the estimated symbolvector and Log-likelihood Ratio (LLR) values for the transmitted bits.The LLR of bit x_(k), the k-th bit of the transmitted bit streams x, isdefined as:

$\begin{matrix}{{{LLR}\left( {xk} \middle| z \right)} = {\ln \; \frac{P\left\lbrack {{xk} = \left. 1 \middle| z \right.} \right\rbrack}{P\left\lbrack {{xk} = \left. 0 \middle| z \right.} \right\rbrack}}} & (3) \\{\approx {{\min\limits_{x\; \in S_{k}^{(1)}}{{z - {Rx}}}^{2}} - {\min\limits_{x \in S_{k}^{(0)}}{{z - {Rx}}}^{2}}}} & (4)\end{matrix}$

Where S_(k) ⁽¹⁾ and S_(k) ⁽⁰⁾ represent all vector x with bit positionx_(k) being “1” and “0”, respectively.

This algorithm can be easily scaled to high-order constellations (e.g.,256-QAM, 1024-QAM) and large number of antennas. The algorithm retains,processes and utilizes paths discarded from the intermediate tree levels(hereinafter, tree level and level will be used alternatively and denotea processing stage in a pipelined architecture, e.g., at each level, thebest paths (K-Best paths) are retained and other paths may be discarded(discarded paths)), in addition to the exhaustively extended paths atthe last tree level, to attain considerable Bit Error Rate (BER)performance improvement compared to the Hard K-Best Detection scheme.

In a 2N_(R)×2N_(T) real-valued MIMO system with channel characteristicmatrix H, the detection task is to find K lowest PED paths per level and√Q children per path in a tree with 2N_(T) levels. The task of a HardK-Best detector is to find the lowest PED 2N_(T)×1 vector at the lastlevel of the tree. On the other hand, the task of a Soft K-Best detectoris to compute LLR values for (2N_(T))(log₂(Q)/2) transmitted bits usingall of the existing paths at the last level and the discarded paths fromthe intermediate levels.

In some embodiments, the K-Best algorithm explores the tree from theroot to the leaves by expanding each level and selecting the K bestcandidates in each level. Let us consider K surviving nodes in level i.Each of these nodes has √Q possible children in level i+1, from thesymmetry in the Q-QAM constellation. The K-Best algorithm visits allthese children and calculates their Partial Euclidean Distances (PED)values resulting in K√Q children at level i+1. Once the PED values arecalculated, the K-Best algorithm sorts all these K√Q children andselects the K best children as the surviving nodes in level i+1. All ofthe existing paths at the last level are considered to calculate the LLRvalues.

An exemplary Soft-output K-Best detection algorithm for computing theLLR values for (2N_(T))(log₂(Q)/2) bits according to an embodiment ofthe present invention is provided below.

(1) Find the K-Best children of level 1. (K₁) (2) For l = 2:1:2N_(T)−L−1(L being the number of tree levels for which  relevant Discarded pathsneed to be collected) (2.1) Find the K-Best paths at level l using theOn-Demand child  expansion scheme (K_(l)). End (3)For l = 2N^(T)−L:1:2N_(T)−1 (3.1) Find the K-Best paths at level l using the On-Demandchild expansion scheme. (3.2) Populate a Bit Occurrences table forsymbols corresponding to  level l −>1 (2*l*(log₂(Q)/2) entries) usingthe K-Best paths K_(l). (3.3) Update the Bit Occurrences table using thediscarded paths  accumulated from all previous levels (D_(l−1 −>1)).Also, copy (D_(l−1−>1)) to  (D_(l−>1)). (3.4) Examine each of the K−1discarded paths at the current level  (D_(l)) and select it for furtherprocessing (add to D_(l−>1)) only if it fills at  least one void entryin the Bit Occurrences table. (3.5) Perform ZF augmentation and PEDupdate for each discarded  path in D_(l−>1) to level l+1.  End (4) Atlevel l = 2N_(T) (4.1) Sort the discarded paths from (D_(2NT−1−>1)) inthe ascending order of PED. (4.2) Extend the K-Best paths at level2N_(T)−1 (K_(2NT−1)) to exactly K  paths at level 2N_(T) using ZFaugmentation. (4.3) Use these K paths at level 2N_(T) to fill the MinPEDtable for the  first (2N_(T)−1)(log₂(Q)/2)bits. (4.4) To compute LLR forthe last (log₂(Q)/2) bits: (4.4.1) Use the lowest PED ZF augmented pathat level 2N_(T) to  fill exactly half the MinPED table for these bits.(4.4.2) Perform On-Demand extension of (K_(2NT−1)) and use at  most 2K−1paths, in the order of ascending PEDs, to fill the rest half of  theMinPED table for these bits.  (5) Use the sorted 2N_(T) x 1 discardedpaths from (D_(2NT−1−>1)) to update  the MinPED table using the RelaxedLLR Computation scheme.  (6) Compute LLR values using the minimum PEDdata in the MinPED  table for each of the 2N_(T)(log₂(Q)/2) transmitted.

According to one embodiment of the present invention, the Soft-outputK-Best MIMO detection approach can implement one or more of theinnovative processes that significantly reduce computational complexitywithout a major sacrifice in bit error rate (BER) performance. Theinnovative processes may include:

1. a Relevant Discarded Paths Selection process;

2. a Last-Stage On-Demand Expansion process; and

3. a Relaxed LLR Computation process.

Relevant Discarded Paths Selection

Due to the On-Demand nature of child expansion, a Hard K-Best schemeonly produces K−1 discarded paths at each tree level. The current SoftK-Best scheme would accumulate these K−1 discarded paths at each treelevel. Hence, assuming that the discarded paths are utilized from L treelevels, a straightforward extension of the Hard K-Best scheme will stillneed to process a total of L(K−1) discarded paths to produce softoutputs.

Let us denote the partial paths at each tree level (paths from root nodeto an intermediate tree level) or the complete paths (paths from rootnode to the last tree level) by x, and a bit position within the path byj. Also denote the Minimum PED (MinPED) for the jth bit in x being ‘0’as MinPED0j and the Minimum PED for the jth bit being ‘1’ as MinPED1j.The following three observations lead to the derivation of the firstimprovement idea, namely: selection and utilization of only relevantdiscarded paths.

1. For the Hard K-Best scheme, the K−1 discarded paths at each treelevel are already sorted according their PED values.2. Among the paths at a particular tree level and for jth bit in thesepaths, a K Best path will definitely yield smaller MinPED0j andMinPED1j, compared to a discarded path at that tree level.3. If a particular discarded path does not provide any extra information(i.e. MinPED for one or more bits), then there is no advantage instoring and ZF augmenting that discarded path.

Based on these observations, the current improvement idea proposes toanalyze the K best paths and the rest of the discarded paths at eachtree level, and only select those discarded paths for further processing(ZF augmentation and LLR computation) that yield MinPED for at least oneof the bits. The rest of the unselected discarded paths at that treelevel should not be stored or processed any further, and hence theyshould be just abandoned. According to one embodiment, the relevantdiscarded paths are selected using the following process at each treelevel:

-   Step 1: First, populate a Bit Occurrences table for the symbols    corresponding to the current tree level and all previous levels,    using the K best paths at the current tree level.-   Step 2: Then, attempt to fill in the remaining entries in the Bit    Occurrences table using the discarded paths accumulated and    forwarded from the previous levels.-   Step 3: At the end, examine each of the sorted discarded paths at    the current level one by one (in the order of ascending PEDs), and    select the current discarded path for further processing only if it    fills at least one of the void entries in the Bit Occurrences table    for the current tree level.

It is noted that for Level k, a bit occurrence table is simply a tableof dimensions 2×(N_(T)−k−1)*(log₂(Q)/2), that keeps track of occurrencesof “0” and “1” values for (NT−k−1)*(log₂(Q)/2) bits (an (N_(T)−k−1)×1real-valued vector) in the K-Best paths and accumulated chosen discardedpaths. Thus, this improvement idea proposes to select and forward onlythe relevant discarded paths that contain useful information for LLRcomputation, out of the total L(K−1) discarded paths. In other words,this improvement idea recognizes and eliminates the irrelevant discardedpaths to reduce the overall computational complexity significantly.Through mathematical analysis, the largest number of selected discardedpaths can be derived to be ((2N_(T)−1)(log₂(Q)/2))−(K−1), for the givenconstellation size, antenna configuration and the value of K. It isnoted that the number of selected discarded paths is the largest in theworst case scenario, when discarded paths are utilized from all of theintermediate tree levels and when all of the K−1 best paths at the lastlevel only yield one different bit from all of the previous K bestpaths. Thus, this improvement idea results in large savings incomputational complexity, since the Soft K-Best detection scheme nowonly needs to ZF augment, compute and compare the PED for a maximum of((2N_(T)−1)(log₂(Q)/2))−(K−1) paths. In one example embodiment, for 4×464-QAM MIMO detector with K=10 and L=6, a maximum of 12 paths need to beprocessed using this improvement idea, as opposed to the 54 discardedpaths processed in the conventional techniques.

Last-Stage On-Demand Expansion

Another major issue with existing Soft K-Best schemes that leads to highcomputational complexity, is the exhaustive expansion of the paths atthe last tree level. In other words, the existing Soft K-Best detectionschemes exhaustively expand the K best paths at the level 2N_(T)−1 toall possible K√Q paths at level 2N_(T). These Soft K-Best schemes thencompute PED for these exhaustively expanded K√Q paths and compare thesePEDs to compute the LLR values. Hence, for large constellations and forlarge values of K, this approach leads to a very large number of PEDcomputations and comparisons. For example, for a 4×4 64-QAM MIMOdetector with K=10, this will require computation and comparison of 80PED values at the last tree level, to compute LLR values for 24transmitted bits. Hence, this causes either large processing latency(defined as the number of cycles required to compute each new set of LLRvalues) for hardware constrained detectors or large hardwarerequirements for high-throughput detectors.

However, through careful analysis, it can be observed that within thecomplete set of K√Q vectors, there are only K distinct 2N_(T)−1×1 symbolvectors, corresponding to the first 2N_(T)−1 levels of the detectiontree. Hence, the exhaustively extended K√Q paths only improve thequality of LLR for the last log₂(Q)/2 transmitted bits, that correspondto the last level of the detection tree. The exhaustive expansion of theK best paths at the level 2N_(T)−1 to K√Q paths at the level 2N_(T) doesnot yield any LLR quality improvement for the first(2N_(T)−1)(log₂(Q)/2) transmitted bits. Thus, the existing approach ofexhaustively extending paths at the last level provides minimal BERperformance gain, while requiring a large amount of extra resources forimplementation.

To resolve these issues, an embodiment of the present invention uses theLast Stage On-Demand Expansion process as described below:

-   Step 1: First, extend (expand) the K best paths at tree level    2N_(T)−1 to exactly K paths at level 2N_(T) using ZF augmentation.-   Step 2: Use these K ZF augmented paths at tree level 2N_(T) to fill    the MinPED table for the first (2N_(T)−1)(log₂(Q)/2) bits, because    for these bits, the K ZF augmented paths at the level 2N_(T) yield    the smallest PED values.-   Step 3: For the last (log 2(Q)/2) bits:    -   3.1: First use the lowest PED ZF augmented path, from the K ZF        augmented paths at level 2N_(T), to fill exactly half of the        MinPED table for the last (log 2(Q)/2) bits.    -   3.2: Then, perform on-demand extension and use at most 2K−1        paths, in the order of ascending PEDs, to fill the remaining        half of the MinPED table.

The Last Stage On-Demand Expansion scheme expands the K paths at thetree level 2N_(T)−1 on-demand to only the 2K−1 relevant paths at level2N_(T) for LLR computation purposes. The on-demand nature of pathextension ensures that these 2K−1 paths have the lowest PED among theK√Q paths. It also ensures that these paths are expanded and utilized tofill the MinPED table in the order of ascending PED. In other words, ifa particular entry in the MinPED table is already filled, there is noneed to compare the current MinPED with the PED for the paths extendedafterward. Hence, this avoids PED comparisons at the last level for thepurpose of filling the MinPED table and LLR computation.

Thus, the Last Stage On-Demand Expansion scheme according to anembodiment of the present invention reduces the number of pathextensions from K√Q to only 2K−1 and reduces the number of PEDcomparisons from K√Q to 0.

Relaxed LLR Computation Scheme

A prior art Modified K-Best Schnorr-Euchner (MKSE) detection schemeperforms LLR computation using the 3-step process shown below:

-   Step 1: First, fill the MinPED table for all N_(T) log₂(Q) bits    using the last level extension of the K-Best paths.-   Step 2: Then, examine each discarded path and compare its PED with    the existing MinPEDs to attempt to fill or update the MinPED table.-   Step 3: Use the minimum PED data in the MinPED table to compute LLR    values (by simply subtracting the MinPEDs) for each of the N_(T)    log₂(Q) transmitted bits.

As can be observed, the second step in this process requires comparisonof each discarded path PED to the current 2N_(T) log₂(Q) MinPEDs. Hence,this leads to a total of (2N_(T) log₂(Q))(L(K−1)) comparisons, which inturn leads to a large computational complexity. However, if anassumption is made that the MinPED values attained by extending theK-Best paths are always smaller compared to the discarded path PEDs,then a large amount of computations can be avoided. This assumption isthe basic idea behind the Relaxed LLR Computation Scheme in oneembodiment of the present invention. One embodiment of the inventiveRelaxed LLR Computation scheme modifies Step 2 in the LLR computationprocess as follows:

Step 2—Modified: For each discarded path, in the ascending order ofPEDs, fill an entry in the MinPED table only if it is still empty.

Thus, the Relaxed LLR Computation Scheme according to one embodiment ofthe present invention does not perform any PED comparisons and fills anentry in the MinPED table, only if that bit was not covered by eitherthe extended K-Best paths or the preceding discarded paths. Hence, thisscheme essentially approximates output LLR values, rather thanperforming exact computation.

However, this assumption is not always valid, and hence might lead todegradation in LLR quality and hence in the resulting detector BERperformance. This might happen in the following case: if for aparticular bit, a discarded path has a smaller PED compared to thecurrent MinPED value for that bit. This case is classified as an errorcase in the LLR computation and its corresponding error probability isquantified by simulating a 4×4 64-QAM MIMO detector for a large numberof transmitted bits.

Referring to FIG. 1, an error percentage plot for a Relaxed LLRComputation scheme according to an embodiment of the present inventionis shown. From the error percentage plot, it can be observed that theprobability of error is higher at low SNR values and reducessignificantly for higher SNR values. This can be explained by noticingthat at low SNR values, the larger noise might cause good vectors to bediscarded on the intermediate stages, which after ZF augmentation to thelast level end up having smaller PED values than the K-Best vectors. Itshould be appreciated that the maximum value of error percentage isapproximately 0.125% and the average is 0.03%. Thus, it can be concludedthat the Relaxed LLR Computation scheme causes only minor LLR qualitydegradation, while reducing computational complexity by a large amount.

According to an embodiment of the present invention, the above discussedapproaches for a low-complexity Soft-output K-Fast MIMO detection can beimplemented using a deeply pipelined and highly parallel architecture.This novel architecture is designed to be area and power efficient,while offering very high detection throughput. Through physicalsynthesis, the novel architecture has been proven to support errorcorrecting codes (ECC) coded data rates up to 1 Gbps with a detectionthroughput of up to 2 Gbps. Thus, this architecture can satisfy theaggressive requirements of the latest 4G wireless standards such as IEEE802.16m and LTE-Advanced.

FIG. 2 shows a simplified block diagram of a 4×4 64-QAM Soft-outputK-Best MIMO detector 200 according to an embodiment of the presentinvention. Detector 200 includes an input terminal configured to receivean R matrix and a Z vector as defined in Equation (2). Using thereal-value decomposition (RVD) scheme, the R matrix after the QRdecomposition is an upper-triangular matrix and has symmetry features.In an embodiment, input entries R and Z are received and buffered inregisters 210. In the example shown, the soft-output K-Best MIMOdetector is described with K=10 and Ω={−7, −5, −3, −1, +1, +3, +5, +7}and four transmit antennas (N_(T)=4). There are thus 2N_(T)=8 treelevels. The first level of the tree (indicated as “L8”), whichcorresponds to the last row of Equation (2), opens up all the possiblevalues in Ω, and calculates their corresponding PED values. The outputof this stage is K1 resulting in |Ω|=8 PED values. For each of the nodesin K₁, the first child is found and its PED is updated using the FC(First Child)-Block in Level II. Detector 200 further includes a Sorterblock that sorts all eight resulting PED values K1′ in four clockcycles, to determine the lowest PED value.

The output of the Sorter block is the sorted FCs (First Children) of L7,i.e., C₂, which are all loaded simultaneously to the next stage PE I(Processing Element I). Note that the dashed gray arrows imply that thedata is loaded only once after the completion of the previous stage, andthe number on them shows how many clock cycles after the completion ofthe previous stage data is loaded. Generally speaking, in each level,one PE II (Processing Element II) block is used to generate and sort thelist of all FCs of the current level and one PE I block is used togenerate the K-Best list of the current level. This fact is denoted inFIG. 2 by FC-Li (First Children in i-th level) and NC-Li (Next Childrenin i-th level) labels under each level's block. The PE I block takes theFCs of each level and uses a PED sorter and a core called NC-Block inthe feedback loop to generate the K-Best paths (indicated as KB) of thatlevel one-by-one. The PE II receives the K-Best candidates of theprevious level, one after the other, and generates the FC of eachreceived K-Best candidate one-by-one, and sorts them as they arrive. Itfinally transfers them to its following PE I block for computation ofthe K-Best paths. Since at the last level only the FC with the lowestPED is of concern, only one PE II block is used for the first level(FC-L1), whose output is the solution to the hard detection symbol Srepresenting the 2N_(T)×1-dimensional transmit vector.

Detector 200 further includes Soft-output processing element (SPE)blocks in intermediate tree levels (indicated as SPE_Li where I=7 to 2).The SPE blocks and DP Sorter blocks together create the discarded path(DP) datapath that only retains selected discarded paths from each treelevel, performs ZF augmentation and PED computation for them and sortsthem. The rest of the unselected discarded paths at that tree levelwon't be stored or processed any further, i.e., discarded. In oneembodiment, the selection of the relevant discarded paths is performedaccording to the three steps of the Relevant Discarded Paths Selectionprocess described above. The SPE block samples in the K-Best paths andK−1 discarded paths from PE I block at each level, as well as theaccumulated selected discarded paths from all of the previous levels. Itthen observes the bit occurrences in the K-Best paths and accumulatedselected discarded paths, and uses this observation to select and tagonly useful discarded paths at the current level. The SPE block thencomputes ZF augmentation for all of the selected discarded paths usingthe FC-Block and updates their PED values. At the last tree level, theoutput of SPE_L2 block consists of only selected discarded paths havingdimensions 2N_(T)×1, that have been fully ZF augmented to the last treelevel. The output of SPE_L2 is coupled to a DP_Sorter block that isconfigured to sort all of the accumulated selected discarded paths inthe order of ascending PEDs to prepare them to be used for LLRcomputation.

Detector 200 further includes a Fill MinPEDTable I block, FillMinPEDTable II block and ComputeLLR Output Controller block connected inseries at the last tree level (indicated as FC_L1). These three blocksperform the task of computing LLR values using the chosen discardedpaths and extended K-Best paths at the last tree level. In oneembodiment, the process of LLR computation can be performed in twosteps. In the first step, the selected discarded paths and extendedK-Best paths can be observed to fill a minimum PED (MinPED) table foreach transmitted bit. In the second step, this MinPED table can be usedto compute LLR values for each bit, by simply subtracting the MinPEDvalues for each bit. In one embodiment, the Fill MinPEDTable I blockinitializes and fills the MinPED table using the 2N_(T)×1 pathsgenerated through the Last Stage On-Demand Expansion process describedabove. The Fill MinPEDTable II block then updates this MinPED tableusing the accumulated selected discarded paths. The ComputeLLROutputController block, which is the final stage of the Soft-outputK-Best detector, computes LLR values for the transmitted bits andoutputs them in parallel using the LLROut 1 and LLROut 2 ports.

FIG. 3 shows a simplified single block diagram of a soft processingelement (SPE_Lk) for Level k according to an embodiment of the presentinvention. SPE_Lk block includes Note Bit Occurrence (NBO_Lk) block, aTag Discarded Path (TDP_Lk) block coupled to the NBO_Lk block, and aFirst Child (FC_L(k−1) block coupled to the TDP_Lk block. The NBO andTDP blocks together implement the Relevant Discarded Paths Selectionprocess described above. The NBO block samples in K-Best paths from thecurrent level (“KB_Lk”) and accumulated ChosenDPs from the previouslevels (“ChosenDP_L7_to_L(k+1)” These K-Best and discarded paths arethen observed and utilized to fill the bit occurrence table at thecurrent level. It is noted that for Level k, a bit occurrence table issimply a table of dimensions 2×(N_(T)−k−1)(log₂(Q)/2), that keeps trackof occurrences of “0” and “1” values for (N_(T)−k−1)(log 2(Q)/2) bits((N_(T)−k−1)×1 real-valued vector) in the K-Best paths and accumulatedChosenDPs. The TDP_Lk block receives current level discarded paths andtags current the discarded paths at the current level if they containinformation that is relevant for computing LLR values of transmittedbits in the next level. The FC_L(k−1) block receives the accumulatedChosenDPs from the previous levels and outputs selected discarded pathsfor the current level. The FC_L(k−1) block is configured to update apartial Euclidean distance (PED) value of a first child using one ormore multiplier blocks that are described in detail below.

Multiplication Block

The overall Soft K-Best detector architecture shown in FIG. 2 involvestwo types of multiplications. The multiplication of ^(˜)z_(i)*r_(ij) ands_(i)*r_(ij). In one embodiment, the first multiplication can berealized using 13-bit×13-bit multipliers, and the second multiplicationcan be implemented using an alternative architecture, which takes lessarea and has a much smaller critical path. FIG. 4 is a block circuitschematic illustrating this architecture using multiplexers having twoinputs and an adder (indicated as “SUM”). As shown in FIG. 4, thenumbers on the right represent the bit location in s_(j) (i.e., s_(j)can be represented with 4 bits), “

n” represents n shifts to the left and the tiny bubble “

” denotes the negation operation. It should be appreciated that all ofthe fixed-point numbers use the two's complement representation.

It should be appreciated that this simple implementation of themultiplication operation, s_(i)*r_(ij), is possible because the valuesof s_(i) are drawn from a finite pre-determined odd-integer setΩ={(−√Q+1), . . . , −1, +1, . . . , (+√Q−1)}, where Q is theconstellation size (or constellation order). The structure of the MUblock is such that the adder always produces one of the odd multiples ofr_(ij) (i.e., r_(ij), 3r_(ij), 5r_(ij), 7r_(ij)), depending on the valueof s_(i). The multiplexers before the adder perform the function ofselecting correct operands for the adder. The first operand of the addercan be either of r_(ij) or −r_(ij), and the second operand of the addercan be any of 0, 2r_(ij), 4r_(ij) or 8r_(ij). The multiplexer in thelast stage, after the adder, utilizes the Most Significant Bit (MSB) ofs_(j) to make the decision on whether or not to negate the outputs_(i)*r_(ij).

This way of implementation of the multiplication operation is muchfaster than a normal multiplier implementation. The motivation fordesigning the MU block is due to the fact that this multiplication liesin the critical path of the architecture, which is on a feedback path.Since the fine-grained pipelining technique cannot be used in thefeedback path to improve the overall throughput, an efficientimplementation of the multiplier using this scheme is critical toenhance the maximum operating frequency for the Soft K-Best detector.

Note Bit Occurrence (NBO) Block

FIG. 5 is a simplified block diagram of a Note Bit Occurrences (NBO)block 500 for Level 6 (NBO_L6) with critical path highlighted accordingto an embodiment of the present invention. The NBO block includes twoparts: a KB Datapath and a DP Datapath. The KB Datapath and DP Datapathparts independently fill the bit occurrence tables for K-Best paths andaccumulated ChosenDPs, respectively, in a completely parallel manner.The logical OR operation at the NBO block output then merges these twoindependent bit occurrence tables. In each of these datapaths, theprocess of filling the bit occurrence table is carried out in two steps.In the first step, the input symbol in binary two's complementrepresentation is converted to its constellation representation. Thesecond step then uses this constellation representation to update thebit occurrence table using the blocks KB_NBO and DP_NBO. The overallcritical path of the NBO block is also shown in FIG. 5, which consistsof MapBin2Constellation Re/Im and DP NBO sub-blocks.

FIG. 6 shows a simplified block diagram of a KB_NBO sub-block accordingto an embodiment of the present invention. The KB_NBO sub-block useslogical XNOR operations with “0” or “1” to determine whether the currentbit is “0” or “1”. In one embodiment, the KB NBO sub-block uses aspecial mechanism to reset the KB bit occurrence table, using thelogical OR and AND operations. This special reset mechanism is requiredsince the KB NBO sub-block needs to be active for all K=10 clock cyclesand there are no idle cycles available for register reset. Hence, KB NBOneeds to be reset in the same clock cycle when the first K-Best path isprocessed.

FIG. 7 shows a simplified block diagram of a DP_NBO sub-block accordingto an embodiment of the present invention. The DP_NBO sub-block useslogical XNOR operations with “0” or “1” to determine whether the currentbit is “0” or “1”. The DP NBO sub-block can be reset by simply resettingregisters 710. In an embodiment, the DP NBO includes a tagging mechanismat its inputs. The tagging mechanism may be implemented using NOR andNAND logical operations and is configured to recognize and tag bits thatare associated with selected relevant discarded paths.

FIG. 8 shows a simplified lock diagram of a Tag Discarded Paths (TDP)block 800 according to an embodiment of the present invention. TDP block800 includes a selector circuit 810 configured to receive 9 (nine)discarded paths and utilizes the bit occurrence table prepared by theNBO block (shown in FIG. 5) to observe and tag each of the 9 discardedpaths at the current level. In other words, a discarded path will beselected for further processing and will be tagged “1” only if it fillsa void entry in the present bit occurrence table. TDP block 800 includesa “Load_BOTable” signal for loading the bit occurrence table intoappropriate DP_TDP sub-blocks 830, from the NBO block outputs. Once thebit occurrence table is loaded, selector circuit 810 selects the currentdiscarded path to be processed. The combination of MapBin2ConstellationRe/Im and DP TDP sub-blocks are then used to compute the tags forindividual bits. In one embodiment, the overall tag for the currentdiscarded path, “CurrentDP Tag”, is computed by using a logical ORoperation.

FIG. 9 shows a simplified logic block diagram of a DP_TDP sub-block fora single bit according to an embodiment of the present invention. TheDP_TDP sub_block detects whether the current discarded path will yielduseful information for LLR computation in future and selects (tags) thediscarded path if it is relevant. The DP_TDP sub_block uses logical XNORoperation coupled with “0” and “1” to determine whether the current bitis “0” or “1” and to update the bit occurrence table. In an embodiment,the complete process of selecting and tagging a discarded path isperformed in a single clock cycle, and hence the critical path for theoverall TDP block contains all of the sub-blocks from the DP inputs tothe “CurrentDP Tag” output signal.

FIG. 10 shows a simplified block diagram of a FILL_MinPEDTable_I blockaccording to an embodiment of the present invention. The FillMinPEDTable I block is the first block, in the set of 3 serial blocksthat perform LLR computation. The Fill MinPEDTable I block performs thetask of initializing and filling the minimum PED (MinPED) table usingthe last level extension of K-Best paths. In other words, the FillMinPEDTable I block samples in ZF augmented 10 2N_(T)×1 K-Best paths,processes them and utilizes them to generate the MinPED table and thecorresponding MinPED tag values. The Fill MinPEDTable I block includes 3sub-blocks: a PE I sub-block, a Part 1 sub-block and a Part 2 sub-block.

In an embodiment, the PE I sub-block is identical to the one used in thehard K-Best datapath, as shown in FIG. 2. It receives the sorted list ofZF augmented 10 K-Best paths at level 2N_(T)−1 and uses an On-Demandpath extension scheme to generate a list of K-Best paths at Level2N_(T). Since the On-Demand expansion scheme uses Schnorr-Euchner (SE)enumeration, the 10 K-Best paths are generated one-by-one, in the orderof ascending PEDs. These K-Best paths are then utilized in the FillMinPEDTable I Part2 sub-block to fill the MinPED table. As shown in FIG.10, Fill_MinPED Table 1 block includes multiplexors 1010, 1020configured to select the current ZF augmented path and transfer them tothe “FC Path1” and “FC Path2” ports at each clock cycle. The FillMinPEDTable I Part1 and Fill MinPEDTable I Part2 sub-blocks then utilizethese ZF augmented K-Best paths (“FC Path1” and “FC Path2”) and theK-Best paths from the PE I sub-block (“KB Path”) to populate the MinPEDtable for N_(T) log₂ (Q) bits and compute their tags.

FIG. 11 shows a simplified single functional block diagram 1100 of aFILL_MinPEDTable II block according to an embodiment of the presentinvention. Single functional block diagram 1100 is configured to storeand update a minimum PED (MinPED) value for j-th bit of i-th transmittedsymbol. In one embodiment, the Fill MinPEDTable II block includes 24instances of this single functional diagram block 1000 and is configuredto perform the task of updating the MinPED table using the PED values ofthe chosen (selected) discarded paths that have been ZF augmented in thelast tree level. As shown in FIG. 11, block diagram 1100 includesMapBin2Constellation Re/Im sub-blocks (indicated as “Map_Re/Im”) thatare configured to attain constellation representation of the “Si”symbols for both “DP_Path1_Si” and “DP_Path2_Si” from the DP_Sorterblock (not shown). These constellation representations are then used asselect signals for a multiplexer 1120 that selects the minimum PED among“DP_Path1_PED” and “DP_Path2_PED”, to generate the “Current_DP_MinPED”value. The two branches on left and right sides of multiplexer 1120perform the task of storing and updating the MinPED for “0” and “1”values of the current bit, respectively. It is noted that since the PEDword-length for K-Best and discarded paths are respective 10 bits and 13bits in one embodiment, the input 10-bit MinPED values from the FillMinPEDTable I block needs to be converted to 13-bit fixed-point format.

In one embodiment, the Fill_MinPEDTable_II block, which includes 25instances of single block 1100, implements the Relaxed LLR Computationprocess described in sections above. It is noted that FIG. 11 also showsthe critical path of the Fill MinPEDTable II block.

In one specific embodiment, it is assumed that the MinPED valuesattained by extending the K-Best paths are smaller than the PED valuesof the discarded path. Hence, there is no need to compare the“Current_DP_MinPED” value with the current MinPED value stored in theMinPED register bank. This results in significant hardware savings sincecomparators are not needed. At the final output of theFill_MinPEDTable_II block, the updated MinPED tags are computed bycomparing the current stored MinPED with 13′b0111111111111. Thesecomputed MinPED tags are then utilized by the subsequentComputeLLR_OutputController block, to significantly ease the process ofLLR computation.

The ComputeLLR Output Controller is the last block in the pipelinedarchitecture of the proposed Soft K-Best MIMO detector. This blockreceives the table of MinPED values, that has been populated using thelast level extension of K-Best paths and the FC augmented selecteddiscarded paths. It uses these MinPED values and their correspondingtags to compute the Log-likelihood Ratio (LLR) values for 24(N_(T)*log₂(Q)=4*log₂(64)=24) transmitted bits.

FIG. 12 shows a block diagram of a ComputeLLR Output Controller block1200 according to an embodiment of the present invention. As shown inFIG. 12, ComputeLLR Output Controller block 1200 is divided into a LLRcomputation part, indicated as Part 1210, and a output controller part,indicated as Part 1220. Part 1210 includes a logic circuitry configuredto compute LLR values using the MinPED table and an interface circuithaving multiplexers configured to generate appropriate values for the“MinPED II Bitj (0/1)” signals. Part 1210 selects MinPED values for oneof the bits each cycle, using the control signal “Sel_MinPEDLivevsStored”, which is set to “0” in cycle 1 and to “1” in cycle 2, ineach set of 2 cycles. Note that the MinPED transfer scheduling betweenthe Fill MinPEDTable II and the ComputeLLR Output Controller blockscreates the need for register banks to sample and store the MinPEDvalues for the second bit. The chosen bit MinPED values for “0” and “1”are then subtracted to compute LLR values using Equation (4). TheComputeLLR Output Controller block then utilizes the MinPED tag valuesto check validity of the computed LLRs and decide on the correct outputLLR values.

Part 1220 functions as an Output Controller to output computed LLRvalues for 24 transmitted bits according to an embodiment of the presentinvention. Part 1220 includes two sets of register banks connected inseries and being configured to reduce the critical path length. Theclock driven multiplexers 1230, 1232 then output two LLR values perclock cycle (one at each of the positive and negative edges of clock) atthe ports “LLROut_(—)1” and “LLROut_(—)2”. Thus, each port in the secondpart of the ComputeLLR Output Controller block outputs 12 LLR valueswithin 6 clock cycles, in each set of 10 cycles.

FIG. 13 is a graph illustrating the BER performance of the presentinvention vs. conventional art for a 4×4 MIMO system with 64-QAM. Fromthe BER curves, it can be noticed that the first innovative scheme,Relevant Discarded Paths Selection, causes the largest BER performancedegradation compared to the other two innovative schemes. The RelevantDiscarded Paths Selection scheme results in approximately 0.4 dB loss atBER=10⁻³, compared to the MKSE detection scheme. This BER degradation isdue to the following case: For a particular bit, ZF augmentation of anunselected discarded path yields smaller final Euclidean distancecompared to the final Euclidean distance for ZF extension of a chosendiscarded path. This error case causes LLR quality degradation, andhence BER performance degradation, compared to the case where all K−1discarded paths at each tree level are forwarded for LLR computation.However, the other two innovative schemes, Last Stage On-demandExpansion and Relaxed LLR Computation, only cause approximately 0.1 dBand 0.04 dB loss at BER=10⁻³, respectively. This is consistent with theobservation made from the Error Percentage plot (FIG. 1) for the RelaxedLLR Computation scheme, that shows that the probability of error isabout 0.03% on average. Thus, in total, for the 64-QAM case, the presentinvention results in 0.54 dB loss compared to the MKSE scheme presentedin Z. Guo and P. Nilsson, “Algorithm and implementation of the K-Bestsphere decoding for MIMO detection,” IEEE Journal on Selected Areas inCommunication, vol. 24, no. 3, pp. 491-503, March 2006 (indicated as“[11]” in FIG. 13), while reducing the number of computations requiredfor LLR calculation by a factor of 5 (five). However, it should beappreciated that the present invention improves the BER performance byabout 1.7 dB and 2.9 dB compared to the conventional Soft K-Best schemeand the Hard K-Best scheme at BER=10⁻³, respectively.

The above embodiments of the present invention are illustrative and notlimiting. Various alternatives and equivalents are possible. Otheradditions, subtractions or modifications are obvious in view of thepresent disclosure and are intended to fall within the scope of theappended claims.

1. A method for soft-output K-Best MIMO detection, the methodcomprising: receiving a vector associated with data bits transmittedover a multiple-input multiple output (MIMO) system, the MIMO systemhaving N transmit antennas, N being an integer greater than unity;processing the received vector using a plurality of processing elements,the processing elements being arranged in a plurality of levels andconnected in series; and computing Log-likelihood Ratio (LLR) values forthe transmitted data bits.
 2. The method of claim 1, wherein theplurality of levels comprises 2N levels.
 3. The method of claim 1further comprising: retaining selected discarded paths from intermediatelevels within the 2N levels; computing partial Euclidean distance (PDE)values in the intermediate levels utilizing the retained selecteddiscarded paths; and sorting the PDE values.
 4. The method of claim 1further comprising a relevant discarded paths selection process, therelevant discarded paths selection process comprising: examining pathsat the intermediate levels; and selecting discarded paths for computingthe LLR values.
 5. The method of claim 1 further comprising a last-stageon-demand expansion process, the last-stage on-demand expansion processcomprising: expanding K paths at a level 2N−1 to 2K−1 paths at a lastlevel 2N, wherein K is an integer greater than zero.
 6. The method ofclaim 5, wherein the 2K−1 paths have the lowest PED values among K*√Qpaths, Q being an integer of a constellation symbol size.
 7. The methodof claim 5, wherein the 2K−1 paths are sorted in the order of ascendingPED values.
 8. The method of claim 1 further comprising a relaxed LLRcomputation process, the relaxed LLR computation process comprising:filling a PED table using K paths having the lowest LLR values in thelast level; and filling empty entries in the PED table with discardedpaths in the ascending order of PED values.
 9. A soft-output K-Bestmultiple input multiple output (MIMO) detector, the detector comprising:an input terminal configured to receive a vector associated withtransmitted bits over a multiple-input multiple output (MIMO) system,the MIMO system having N transmit antennas, N being an integer greaterthan unity; a plurality of processing elements connected in series andarranged in a plurality of levels, the processing elements beingconfigured to compute Log-likelihood Ratio (LLR) values for thetransmitted bits.
 10. The soft-output K-Best MIMO detector of claim 9,wherein the plurality of levels comprises 2N levels.
 11. The soft-outputK-Best MIMO detector of claim 9 further comprising an output terminalhaving two output ports configured to output the computed LLR values ofthe transmitted bits in parallel.
 12. The soft-output K-Best MIMOdetector of claim 9, wherein the plurality of processing elements isconfigured to: retain selected discarded paths from intermediate levelswithin the plurality of levels; compute partial Euclidean distance (PED)values in the intermediate levels utilizing the retained selecteddiscarded paths; and sort the PED values.
 13. The soft-output K-BestMIMO detector of claim 9, wherein the plurality of processing elementsis configured to: examine paths at intermediate levels within theplurality of levels; and select discarded paths for computing LLRvalues.
 14. The soft-output K-Best MIMO detector of claim 9, wherein theplurality of processing elements is configured to: expand K paths at alevel 2N−1 to 2K−1 paths at a last level 2N, wherein K is an integergreater than zero.
 15. The soft-output K-Best MIMO detector of claim 14,wherein the 2K−1 paths have the lowest PED values among K*√Q paths, Qbeing a size of a constellation symbol.
 16. The soft-output K-Best MIMOdetector of claim 14, wherein the 2K−1 paths are sorted in the order ofascending PED values.
 17. The soft-output K-Best MIMO detector of claim9, wherein the plurality of processing elements is configured to: fill aPED table using K best paths in a last level; and fill empty entries inthe PED table with discarded paths in the ascending order of PED values;wherein the K best paths comprise the lowest LLR values in the lastlevel.
 18. A device for soft-output K-Best MIMO detection for a MIMOreceiver that receives data bits transmitted over a multiple inputmultiple output (MIMO) system, wherein each transmitted data bit isassociated with a Log-likelihood ratio (LLR) value that is computedbased on a pipelined structure having a plurality of levels, the devicecomprising: a Note Bit Occurrences (NBO) block configured to receivefirst selected discarded paths of a previous level and populate a bitoccurrence table using current level K-best paths and the received firstselected discarded paths of the previous levels; a Tag Discarded Paths(TDP) block coupled to the NBO block and being configured to receivecurrent level discarded paths and tag a current discarded path using thebit occurrence table; a First Child (FC) block coupled to the TDP blockand being configured to receive the first selected discarded paths ofthe previous level and provide second selected discarded paths for acurrent level; a first partial Euclidean distance (PED) table blockcoupled to the FC block and being configured to populate a minimum PEDtable; and a second PED table block coupled to the first PED table blockand being configured to update the minimum PED table using the secondselected discarded paths for the current level.
 19. The device of claim18 further comprising an output controller block coupled to the secondPD table block and being configured to compute the LLR value for eachtransmitted bit using the updated minimum PED table
 20. The device ofclaim 18, wherein the FC block updates a partial Euclidean distance(PED) value of a first child using one or more multiplier block, each ofthe one or more multiplication blocks comprises one adder and fourmultiplexor circuits being configured to perform multiplication ofoperands with any of −7, −5, −3, −1, +1, +3, +5 or +7 representing realand imaginary parts of a constellation symbol.
 21. The device of claim18, wherein the Tag Discarded Paths (TDP) block determines whether thecurrent discarded path provides information data for computingLog-likelihood ratio (LLR) values of transmitted bits in a next stage;and in the event that the current discarded path provides theinformation data for computing LLR values, tag the current discardedpath.
 22. The device of claim 18 further comprising an output controllerblock configured to compute Log-likelihood ratio (LLR) values fortransmitted bits.